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NCP5351 4 A Synchronous Buck Power MOSFET Driver
The NCP5351 is a dual MOSFET gate driver optimized to drive the gates of both high- and low-side Power MOSFETs in a Synchronous Buck converter. The NCP5351 is an excellent companion to multiphase controllers that do not have integrated gate drivers, such as ON Semiconductor's CS5323, CS5305 or CS5307. This architecture provides a power supply designer the flexibility to locate the gate drivers close to the MOSFETs. 4 Amp drive capability makes the NCP5351 ideal for minimizing switching losses in MOSFETs with large input capacitance. Optimized internal, adaptive nonoverlap circuitry further reduces switching losses by preventing simultaneous conduction of both MOSFETs. The floating top driver design can accommodate MOSFET drain voltages as high as 25 V. Both gate outputs can be driven low, and supply current reduced to less than 25 A, by applying a low logic level to the Enable (EN) pin. An Undervoltage Lockout function ensures that both driver outputs are low when the supply voltage is low, and a Thermal Shutdown function provides the IC with overtemperature protection. The NCP5351 is pin-to-pin compatible with the SC1205 and is available in a standard SO-8 package. Features * 4 A Peak Drive Current * Rise and Fall Times < 15 ns Typical into 6000 pF * Propagation Delay from Inputs to Outputs < 20 ns * Adaptive Nonoverlap Time Optimized for Large Power MOSFETs * Floating Top Driver Accommodates Applications Up to 25 V * Undervoltage Lockout to Prevent Switching when the Input Voltage is Low * Thermal Shutdown Protection Against Overtemperature * < 1 mA Quiescent Current - Enabled * 25 A Quiescent Current - Disabled * Internal TG to DRN Pulldown Resistor Prevents HV Supply-Induced Turn On of High-Side MOSFET
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1 SO-8 D SUFFIX CASE 751 1 A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week 8 5351 ALYW
8
PIN CONNECTIONS
DRN TG BST CO 1 8 PGND BG VS EN
ORDERING INFORMATION
Device NCP5351D NCP5351DR2 Package SO-8 SO-8 Shipping 98 Units/Rail 2500 Tape & Reel
Semiconductor Components Industries, LLC, 2002
1
December, 2002 - Rev. 7
Publication Order Number: NCP5351/D
NCP5351
BST VS + - + - 4.25 V Delay Nonoverlap Control Level Shifter TG
DRN
EN
Delay Thermal Shutdown VS
CO PGND
Figure 1. Block Diagram
Table 1. Input-Output Truth Table
EN L H H H H CO X L H L H DRN X < 3.0 V < 3.0 V > 5.0 V > 5.0 V TG L L H L H BG L H L L L
VCO tpdlBG tpdlTG tfTG
VTG-VDRN trTG tpdhTG (Nonoverlap) VBG tfBG trBG tpdhBG (Nonoverlap) VDRN 4.0 V
Figure 2. Timing Diagram
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2
+ -
4.0 V
BG
NCP5351
MAXIMUM RATINGS*
Rating Operating Junction Temperature, TJ Package Thermal Resistance: Junction to Case, RJC Junction to Ambient, RJA Storage Temperature Range, TS Lead Temperature Soldering: MSL Rating *The maximum package power dissipation must be observed. 1. 60 seconds maximum above 183C. NOTE: This device is ESD sensitive. Use standard ESD precautions when handling. Reflow: (SMD styles only) (Note 1) Value Internally Limited 45 165 -65 to 150 230 peak 1 Unit C C/W C/W C C -
MAXIMUM RATINGS
Pin Symbol VS BST DRN Pin Name Main Supply Voltage Input Bootstrap Supply Voltage Input Switching Node (Bootstrap Supply Return) High-Side Driver Output (Top Gate) Low-Side Driver Output (Bottom Gate) TG & BG Control Input Enable Input Ground VMAX 6.3 V 25 V wrt/PGND 6.3 V wrt/DRN 25 V VMIN -0.3 V -0.3 V wrt/DRN -1.0 V DC -5.0 V for 100 ns -6.0 V for 20 ns -0.3 V wrt/DRN -0.3 V -0.3 V -0.3 V 0V ISOURCE NA NA 4.0 A Peak (< 100 s) 250 mA DC 4.0 A Peak (< 100 s) 250 mA DC 4.0 A Peak (< 100 s) 250 mA DC 1.0 mA 1.0 mA 4.0 A Peak (< 100 s) 250 mA DC ISINK 4.0 A Peak (< 100 s) 250 mA DC 4.0 A Peak (< 100 s) 250 mA DC NA
TG BG CO EN PGND NOTE:
25 V wrt/PGND 6.3 V wrt/DRN 6.3 V 6.3 V 6.3 V 0V
4.0 A Peak (< 100 s) 250 mA DC 4.0 A Peak (< 100 s) 250 mA DC 1.0 mA 1.0 mA NA
All voltages are with respect to PGND except where noted.
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NCP5351
ELECTRICAL CHARACTERISTICS (0C < TJ < 125C; VS = 5.0 V; 4.0 V < VBST < 25 V; VEN = VS; unless otherwise noted.)
Parameter DC OPERATING SPECIFICATIONS Power Supply VS Quiescent Current, Operating VBST Quiescent Current, Operating Quiescent Current, Non-Operating Undervoltage Lockout Start Threshold Hysteresis CO Input Characteristics High Threshold Low Threshold Input Bias Current EN Input Characteristics High Threshold Low Threshold Input Bias Current Thermal Shutdown Overtemperature Trip Point Hysteresis High-Side Driver Peak Output Current Output Resistance (Sourcing) - Duty Cycle < 2.0%, Pulse Width < 100 s, TJ = 125C, VBST - VDRN = 4.5 V, VTG = 4.0 V + VDRN Duty Cycle < 2.0%, Pulse Width < 100 s, TJ = 125C, VBST - VDRN = 4.5 V, VTG = 0.5 V + VDRN - - 4.0 0.5 - - A - - - - 170 30 - - C C Both outputs respond to CO Both outputs are low, independent of CO 0 < VEN < VS 2.0 - - - - 0 - 0.8 10 V V A 0 < VCO < VS - - 2.0 - - - - 0 - 0.8 1.0 V V A CO = 0 V CO = 0 V 4.05 - 4.25 275 4.48 - V mV VCO = 0 V, 4.5 V; No output switching VCO = 0 V, 4.5 V; No output switching VEN = 0 V; VCO = 0 V, 4.5 V - - - 1.0 50 - - - 25 mA A A Test Conditions Min Typ Max Unit
Output Resistance (Sinking)
-
0.42
-
Low-Side Driver Peak Output Current Output Resistance (Sourcing) Output Resistance (Sinking) - Duty Cycle < 2.0%, Pulse Width < 100 s, TJ = 125C, VS = 4.5 V, VBG = 4.0 V Duty Cycle < 2.0%, Pulse Width < 100 s, TJ = 125C, VS = 4.5 V, VBG = 0.5 V - - - 4.0 0.6 0.42 - - - A
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NCP5351
ELECTRICAL CHARACTERISTICS (continued) (0C < TJ < 125C; VS = 5.0 V; 4.0 V < VBST < 25 V; VEN = VS, CLOAD = 5.7 nF;
unless otherwise noted.) Parameter Symbol Test Conditions Min Typ Max Unit
AC OPERATING SPECIFICATIONS High-Side Driver Rise Time Fall Time Propagation Delay Time, TG Going High (Nonoverlap Time) Propagation Delay Time, TG Going Low Low-Side Driver Rise Time Fall Time Propagation Delay Time, BG Going High (Non-Overlap Time) Propagation Delay Time, BG Going Low Undervoltage Lockout VS Rising tpdhUVLO EN = VS, CO = 0 V, dVS/dt > 1.0 V/s, from 4.0 V to 4.5 V, time to BG > 1.0 V, TJ = 125C EN = VS, CO = 0 V, dVS/dt < -1.0 V/s, from 4.5 V to 4.0 V, time to BG < 1.0 V, TJ = 125C - 30 - s trBG tfBG tpdhBG TJ = 125C TJ = 125C TJ = 125C - - 25 10 12 55 15 20 80 ns ns ns trTG tfTG tpdhTG VBST - VDRN = 5.0 V, TJ = 125C VBST - VDRN = 5.0 V, TJ = 125C VBST - VDRN = 5.0 V, TJ = 125C - - 30 8.0 14 45 16 21 60 ns ns ns
tpdlTG
VBST - VDRN = 5.0 V, TJ = 125C
-
18
37
ns
tpdlBG
TJ = 125C
-
10
18
ns
VS Falling
tpdlUVLO
-
500
-
s
PACKAGE PIN DESCRIPTION
Pin Number 1 2 3 Pin Symbol DRN TG BST Description The switching node common to the high and low-side FETs. The high-side (TG) driver and supply (BST) are referenced to this pin. Driver output to the high-side MOSFET gate. Bootstrap supply voltage input. In conjunction with a Schottky diode to VS, a 0.1 F to 1.0 F ceramic capacitor connected between BST and DRN develops supply voltage for the high-side driver (TG). Logic level control input produces complementary output states - no inversion at TG; inversion at BG. Logic level enable input forces TG and BG low, and supply current to 10 A when EN is low. Power supply input. A 0.1 F to 1.0 F ceramic capacitor should be connected from this pin to PGND. Driver output to the low-side (synchronous rectifier) MOSFET gate. Ground.
4 5 6 7 8
CO EN VS BG PGND
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5
ATX 12 V
+
5.0 V
12 V
3.3 V
ENABLE
6 VS 4 CO 5 EN 8 3 2 1 7
+
VCORE GND
32
31
30
29
28
27
26
1 2 3 4 5 6 7 8 17 18 19 21 20 22 23
25
VID5 VID0 VID1
BST TG DRN PGND BG NCP5351
VID2 VID3 VID4 NCP5314
6 VS 4 CO 5 EN 8
3.3 V
VID1 VID0 VID5 ENABLE CS2N CS2P CS1N CS1P ILIM 24 BST TG DRN PGND BG NCP5351
3 2 1 7
NCP5351
9
10
11
12
13
14
15
Figure 3. Application Diagram
16
SGND VDRP VFB COMP CS4N CS4P CS3N CS3P
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6 VS 4 CO 5 EN 8
6 SGND Near Socket VFFB Connection NTC Near Inductor
PWRGD
VID2 VID3 VID4 PWRLS VFFB SS PWRGD DRVON ROSC VCC GATE1 GATE2 GATE3 GATE4 GND
BST TG DRN PGND BG NCP5351
3 2 1 7
6 VS 4 CO 5 EN 8
BST TG DRN PGND BG NCP5351
3 2 1 7
NCP5351
APPLICATIONS INFORMATION Theory Of Operation
Enable Pin
The Enable pin is controlled by a logic level input. With a logic level high on the EN pin, the output states of the drivers are controlled by applying a logic level voltage to the CO pin. With a logic level low both gates are forced low. By bringing both gates low when disabling, the output voltage is prevented from ringing below ground, which could potentially cause damage to the microprocessor or the device being powered.
Undervoltage Lockout
the drain (switch node) is sampled and the BG is disabled for a fixed delay time (tpdhBG) after the drain drops below 4 V, thus eliminating the possibility of shoot-through. When the bottom MOSFET is turning off, TG is disabled for a fixed delay (tpdhTG) after BG drops below 2 V. (See Figure 2 for complete timing information). Layout Guidelines When designing any switching regulator, the layout is very important for proper operation. The designer should follow some simple layout guidelines when incorporating gate drivers in their designs. Gate drives experience high di/dt during switching and the inductance of gate drive traces should be minimized. Gate drive traces should be kept as short and wide as practical and should have a return path directly below the gate trace. The use of a ground plane is a desirable way to return ground signals. Also, component location will make a difference. The boost and the VS capacitor are the most critical and should be placed as close as possible to the driver IC pins, as shown in Figure 4(a), C21 and C17.
The TG and BG are held low until VS reaches 4.25 V during startup. The CO pin takes control of the gates' states when the VS threshold is exceeded. If VS decreases 300 mV below threshold, the output gate will be forced low and remain low until VS rises above startup threshold.
Adaptive Nonoverlap
The Adaptive Nonoverlap prevents a condition where the top and bottom MOSFETs conduct at the same time and short the input supply. When the top MOSFET is turning off,
5V D32 BAT54 C21 1.0 F
12 V
GATE1 4 CO 3 BST 2 TG 1 DRN U3 Gate Driver Q7 80NO2
NCP5351 5 EN 6 VS 7 BG 8 PGND Q9 80NO2
DRVON R33 2.2 (a) (b) C17 1.0 F
Figure 4. Proper Layout (a), Component Selection (b)
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NCP5351
TYPICAL PERFORMANCE CHARACTERISTICS
R1 1.0 k COM HOT VS EN CO NCP5351 BST TG BG C1 C2 C3 C4 1.0 F 1.0 F 100 nF 100 nF *Applied after power up and input.
Measurement
R2* 0.108
PGND DRN -5.0 V
Conditions: BST - DRN = 5.0 V; Room Temperature; Oscilloscope referenced to VS (5.0 V).
Figure 5. Top Gate Sinking Current from 0.108 W
Input Pulse 50 ns 0V -5.0 V
CO
0V -5.0 V 0V TG -5.0 V
Figure 6. Top Gate Sinking
Measurement
R1 1.0 k NCP5351 COM HOT R3 50 C2 1.0 F VS EN BST
R2* 0.108
TG BG
DRN PGND CO
C1 1.0 F
-5.0 V Conditions: VS = 5.0 V; Room Temperature; CO = 0 V.
*Applied after power up and input.
Figure 7. Bottom Gate Sinking Current from 0.108 W
Input Pulse 50 ns -3.5 V -4.5 V
DRN -3.5 V -4.5 V 0V BG -0.5 V
Figure 8. Bottom Gate Sinking
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NCP5351
TYPICAL PERFORMANCE CHARACTERISTICS
+5.0 V R1 1.0 k VS EN CO NCP5351 BST TG BG C1 C2 C3 C4 1.0 F 1.0 F 100 nF 100 nF
Measurement Measurement
+ -
PGND DRN
R2* 0.108
*Applied after power up and input.
Conditions: VS = 5.0 V; Room Temperature; DRN = 0 V.
Figure 9. Bottom Gate Sourcing Current into 0.108 W
CO 0 BG 0 +5.0 V 0V
Input Pulse 50 ns
Figure 10. Bottom Gate Sourcing
+5.0 V R1 1.0 k VS EN CO NCP5351 BST TG BG C1 C2 C3 C4 1.0 F 1.0 F 100 nF 100 nF
+ -
PGND DRN
R2* 0.108
*Applied after power up and input.
Conditions: BST - DRN = 5.0 V; Room Temperature; DRN = 0 V.
Figure 11. Top Gate Sourcing Current into 0.108 W
CO 0 TG 0 +5.0 V 0V
Input Pulse 50 ns
Figure 12. Top Gate Sourcing
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NCP5351
TYPICAL PERFORMANCE CHARACTERISTICS
+5.0 V R1 1.0 k VS NCP5351 EN CO R2 50 BST TG DRN BG C4 100 nF
Measurements
C2 10 F
Gated Pulse Burst (2)
C1 10 F
C3 100 nF
PGND + -
Input Pulse
+ -
tpdlBG tpdlTG 4.0 V DRN CO TG BG tpdhTG (non-overlap) tpdhBG (non-overlap)
Figure 13. Nonoverlap Test Configuration
Conditions: VS = 5.0 V; BST - DRN = 5.0 V; CLOAD = 5.7 nF; Room Temperature.
Conditions: VS = 5.0 V; BST - DRN = 5.0 V; CLOAD = 5.7 nF; Room Temperature.
Figure 14. Top Gate Rise Time
Figure 15. Top Gate Fall Time
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NCP5351
TYPICAL PERFORMANCE CHARACTERISTICS
Conditions: VS = 5.0 V; BST - DRN = 5.0 V; CLOAD = 5.7 nF; Room Temperature.
Conditions: VS = 5.0 V; BST - DRN = 5.0 V; CLOAD = 5.7 nF; Room Temperature.
Figure 16. Bottom Gate Fall Time
Figure 17. Bottom Gate Rise Time
+5.0 V VS Input Pulse 60 ns +5.0 V 0V + - EN CO NCP5351 BST
Measurements
TG BG C3 5.7 nF
PGND DRN
C4 5.7 nF
C1 100 nF
C2 100 nF
Figure 18. Bottom Gate and Top Gate Rise/Fall Time Test
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NCP5351
PACKAGE DIMENSIONS
SO-8 D SUFFIX CASE 751-07 ISSUE AA
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
-X- A
8 5
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative.
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NCP5351/D

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